1. Field of the Invention
The present invention relates to a semiconductor memory device and, particularly, to a semiconductor memory device capable of operating synchronously with the rising and falling edges of an external clock and reading data at high speed.
2. Description of the Background Art
Among synchronous dynamic random access memories (SDRAMs) operating synchronously with a clock signal supplied from the outside, one which inputs/outputs data synchronously with the rising and falling edges of an external clock signal is called a double data rate synchronous dynamic random access memory (DDR SDRAM). The DDR SDRAM has already been standardized. The DDR SDRAM of the first generation among the standardized DDR SDRAMs is called a DDR-I.
FIG. 36 is an operation waveform chart showing data output timings in the case of reading data from a DDR SDRAM called DDR-I.
The operation waveform chart of FIG. 36 shows a case where CAS latency CL is 2.5 and a burst length BL is 4. The CAS latency denotes the number of cycles (each cycle starts at the rising edge of an external clock signal EXTCLK and ends at the next rising edge) in a period from a DDR SDRAM receives a command READ (command for reading data) from the outside at time t3 until read data is started to be output at time t8. The burst length denotes the number of bits of data successively read in the period from time t8 to t12 in response to command READ.
The DDR SDRAM outputs data DQ as read data and a data strobe signal DQS synchronously with external clock signals EXTCLK and EXTZCLK. External clock signal EXTZCLK is a clock signal complementary to external clock signal EXTCLK. Data strobe signal DQS is a signal used as a timing of latching data DQ on an external controller side for receiving data DQ.
FIG. 37 is a schematic block diagram for explaining a clock transmission path from a DLL circuit 1500 in a conventional DDR SDRAM to a data output circuit 1550.
Referring to FIG. 37, DLL circuit 1500 outputs a clock signal CLK_PF at a timing earlier than the rising edge of external clock signal EXTCLK by predetermined time, and a clock signal CLK_NF at a timing earlier than the rising edge of external clock signal EXTZCLK by predetermined time. The predetermined time is expressed as a backward amount Ta in FIGS. 40 and 42 which will be described later. A repeater 1520 amplifies the signal level of each of clock signals CLK_PF and CLK_NF and outputs clock signals CLK_P and CLK_N.
A plurality of data output circuits 1550 are provided based on a word configuration to which the DDR SDRAM is adapted. FIG. 37 shows a case where 16 data output circuits 1550 for outputting data signals DQ0 to DQ15, respectively, are provided in a semiconductor memory device.
Each of data output circuits 1550 latches data read from a memory cell array to a data bus DB in accordance with an internal signal NZPCNT determined on the basis of the CAS latency and clock signals CLK_P and CLK_N, amplifies the data, and outputs amplified data.
As shown in FIG. 37, generally, a signal path from DLL circuit 1500 to data output circuit 1550 has a tree shape. The circuits and interconnections disposed so that data output timings of plural data output circuits 1550 are not largely different from each other. Generally, one repeater 1520 is disposed per eight data output circuits or four data output circuits.
FIG. 38 is a block diagram showing the configuration of data output circuit 1550 in FIG. 37.
Referring to FIG. 38, data output circuit 1550 includes: an amplifying circuit 1554 for amplifying a data signal transmitted via data bus DB; a parallel/serial converting circuit 1556 for rearranging plural data supplied in a group from amplifying circuit 1554; an output data latch 1558 for latching an output of parallel/serial converting circuit 1556; an output driver 1530 for outputting data signal DQ to a terminal in accordance with an output of output data latch 1558; and a clock generating circuit 1552 for supplying clocks to amplifying circuit 1554, parallel/serial converting circuit 1556, and output data latch 1558.
Clock generating circuit 1552 outputs signals CLKQ, CQP, CQN, CLKO, and ZCLKO in accordance with clock signals CLK_P and CLK_N supplied from DLL circuit 1500 via repeater 1520 in FIG. 37 and internal signal NZPCNT determined on the basis of the CAS latency.
Amplifying circuit 1554 includes an amplifier RA0 for amplifying data signals transmitted via data buses DB0 and ZDB0 and outputting amplified signals to read data buses RD0 and ZRD0 and an amplifier RA1 for amplifying data signals transmitted via data buses DB1 and ZDB1 and outputting amplified signals to read data buses RD1 and ZRD1.
Data bus DB0 in FIG. 38 is one of data buses DB0 less than 0 greater than  to DB0 less than 15 greater than  in FIG. 37, and data bus DB1 in FIG. 38 is one of data buses DB1 less than 0 greater than  to DB1 less than 15 greater than  in FIG. 37. xe2x80x9cZxe2x80x9d attached to the head of a signal name or data bus name denotes a complementary or inversion signal, and data bus ZDB0 indicates a data bus complementary to data bus DB0. Similarly, data bus ZDB1 denotes a data bus complementary to data bus DB1. By using a pair of complementary data buses, data transmission can be performed by a signal of a small amplitude.
2-bits data read from the memory cell array to the pair of data buses DB0 and ZDB0 and the pair of data buses DB1 and ZDB1 is transmitted as complementary data signals of a small amplitude.
In the case of the DDR-I, data is read from the memory cell array in the external clock cycles on condition that a 2-bits prefetch operation of reading 2-bits data to each data output circuit in a single reading operation is performed. Specifically, data of two bits is read in a group from the memory cell array and output to data output circuit 1550 every cycle of the external clock. In data output circuit 1550, the 2-bits data is ordered and output to the outside every half cycle of the external clock.
Amplifier RA0 operates in the cycles of the external clock synchronously with clock signal CLKQ supplied from clock generating circuit 1552, amplifies the data signals read from the memory cell array to data buses DB0 and ZDB0, and outputs the resultant signals to parallel/serial converting circuit 1556.
In a manner similar to amplifier RA0, amplifier RA1 operates in the cycles of the external clock synchronously with clock signal CLKQ. Amplifier RA1 amplifies the data signals read from the memory cell array to data buses DB1 and ZDB1 at the same timing as that of reading data signals to data buses DB0 and ZDB0, and outputs the amplified data signals to parallel/serial converting circuit 1556.
Parallel/serial converting circuit 1556 orders data of two bits received from amplifiers RA0 and RA1 and outputs the resultant to output data latch 1558.
Output data latch 1558 operates in half cycles of the external clock synchronously with clock signals CLKO and ZCLKO supplied from clock generating circuit 1552, latches the data signals received via read data buses RDD and ZRDD from parallel/serial converting circuit 1556, and outputs signals ZRDH and ZRDL.
Output driver 1530 outputs data signal DQ to drive a terminal in accordance with signals ZRDH and ZRDL which change every half cycle of the external clock.
When data is ordered by parallel/serial converting circuit 1556, the least significant bit (LSB) CA0 of a column address supplied together with command READ to the semiconductor memory device is referred to. In FIG. 38, a signal EZORG obtained by properly shifting address bit CA0 in accordance with the CAS latency is used by parallel/serial converting circuit 1556.
Since 2-bits prefetch operation is performed, one more address is generated internally from the column address supplied from the outside. In the case where address bit CA0 is 0, an xe2x80x9ceven-numberxe2x80x9d address corresponding to the column address supplied and an xe2x80x9codd-numberxe2x80x9d address obtained by incrementing the column address by one are generated on the inside.
On the other hand, in the case where address bit CA0 is 1, an xe2x80x9codd-numberxe2x80x9d address corresponding to the column address supplied and an xe2x80x9ceven-numberxe2x80x9d address obtained by incrementing the column address by one are generated on the inside.
Data corresponding to the xe2x80x9ceven-numberxe2x80x9d address is output to the pair of data buses DB0 and ZDB0 and data corresponding to the xe2x80x9codd-numberxe2x80x9d address is output to the pair of data buses DB1 and ZDB1.
In the case where address bit CA0 is 0, signal EZORG is set to H level. After data is read from the memory array, parallel/serial converting circuit 1556 first outputs data transmitted via read data buses RD0 and ZRD0 to read data buses RDD and ZRDD and, subsequently, outputs data transmitted via read data buses RD1 and ZRD1 to read data buses RDD and ZRDD.
On the other hand, in the case where address bit CA0 is 1, signal EZORG is set to L level. Parallel/serial converting circuit 1556 first outputs data transmitted via read data buses RD1 and ZRD1 to read data buses RDD and ZRDD and, subsequently, outputs data transmitted via read data buses RD0 and ZRD0 to read data buses RDD and ZRDD.
In such a manner, the parallel-to-serial converted data is transmitted to output data latch 1558 and output from a pad to the outside via output driver 1530.
FIG. 39 is a circuit diagram showing the configuration of amplifying circuit 1554 in FIG. 38.
Referring to FIG. 39, amplifying circuit 1554 includes: a signal generating unit 1752 for generating a plurality of timing signals in accordance with control signals OEG, RDETG, and DOE; an inverter 1753 for receiving and inverting a clock signal CK; amplifier RA1 for amplifying data signals transmitted on read data buses RD1 and ZRD1; amplifier RA0 for amplifying data signals transmitted on read data buses RD0 and ZRD0; a connecting circuit 1812 for connecting data buses DB1 and ZDB1 to amplifier RA1 in accordance with signal ZRDAI; and a connecting circuit 1813 for connecting data buses DB0 and ZDB0 to amplifier RA0 in accordance with signal ZRDAI.
Control signal OEG is a signal for instructing a valid data output period. Control signal RDETG is a signal for determining a connection period of the data buses and amplifiers RA0 and RA1. Control signal DOE is a signal for determining an active period of data output circuit 1550.
Signal generating unit 1752 includes: an inverter 1762 for receiving and inverting clock signal CLKQ and outputting a signal ZCK; an inverter 1764 for receiving and inverting signal ZCK and outputting signal CK; a delay circuit 1766 for delaying signal CK by delay time Td; an inverter 1768 for receiving and inverting an output of delay circuit 1766; and an inverter 1770 for receiving and inverting an output of inverter 1768 and outputting signal CKD.
Signal generating unit 1752 further includes: an NAND circuit 1732 for receiving signals RDETG and DOE; an inverter 1734 for receiving and inverting an output of NAND circuit 1732 and outputting signal RDETL; an NAND circuit 1784 for receiving signals RDETL and OE; an NOR circuit 1786 for receiving an output of NAND circuit 1784 and signal CKD and outputting a signal ZRDAI; an NAND circuit 1788 for receiving clock signal CLKQ and signal OE and outputting a signal ZRDAE; and an inverter 1790 for receiving and inverting signal ZRDAE and outputting a signal RDAE.
Signal generating unit 1752 further includes: an inverter 1792 for receiving and inverting signal RDETL; an inverter 1794 for receiving and inverting signal OEG; P-channel MOS transistors 1796, 1798, and 1800 connected in series between a power supply node and a node N100; N-channel MOS transistors 1802 and 1804 connected in series between node N100 and a ground node; an NAND circuit 1804 whose one input is connected to node N100 and whose other input receives signal DOE and which outputs a signal ZOE; and an inverter 1808 for receiving and inverting signal ZOE. An output of inverter 1808 is supplied to node N100 and signal OE is output from node N100.
To the gates of P-channel MOS transistors 1796, 1798, and 1800, an output of inverter 1792, clock signal CK, and an output of inverter 1794 are supplied, respectively. To the gates of N-channel MOS transistors 1802 and 1804, an output of inverter 1794 and signal ZCK are supplied, respectively.
When signal ZRDAI becomes H level, connecting circuit 1812 connects data buses DB1 and ZDB1 to nodes N101 and N102, respectively. When signal ZRDAI becomes H level, connecting circuit 1813 connects data buses DB0 and ZDB0 to nodes N103 and N104, respectively.
Amplifier RA0 includes: a connecting circuit 414 for connecting nodes N103 and N104 to read data buses RD0 and ZRD0 when signal ZRDAE becomes H level; an enable circuit 416 for connecting read data buses RD0 and ZRD0 to the ground node when signal ZOE becomes H level; an initializing circuit 418 for coupling read data buses RD0 and ZRD0 to a ground potential in accordance with signal CKD and an output of inverter 1753; and a sense amplifier 420 which is activated to amplify a potential difference between read data buses RD0 and ZRD0 when signal ZRDAE is at L level and signal RDAE becomes H level.
Amplifier RA1 has a circuit configuration similar to that of amplifier RA0 except that amplifier RA1 is connected to nodes N101 and N102 in place of nodes N103 and N104 and is connected to read data buses RD1 and ZRD1 in place of read data buses RD0 and ZRD0. Consequently, description of the circuit configuration will not be repeated.
FIG. 40 is an operation waveform chart for explaining the operation of amplifying circuit 1554 illustrated in FIG. 39.
Referring to FIGS. 39 and 40, the operation in the case where CAS latency is 2.5 and the burst length is 4 will be described. Signal OEG is a signal for instructing a valid data output period. Signal RDETG is a signal determining a period of connection between the data bus and the amplifying circuit. Signals OEG and RDETG are supplied from a not illustrated control circuit together with signal DOE which determines an active period of the output circuit.
When command READ is given at time t1, outputting of data is started at time t6 after 2.5 clock cycles. Signal DOE is held at H level for a period from command READ is received until the end of a burst period.
In the period from time t4 to t5, signal RDETG becomes H level and signal OEG becomes H level. This indicates a period in which valid data exists on data buses DB0, DB1, ZDB0, and ZDB1. During this period, signal ZRDAI is activated to H level. In response to activation of signal ZRDAI, data buses DB0, DB1, ZDB0, and ZDB1 are connected to read data buses RD0, RD1, ZRD0, and ZRD1, respectively.
In the period from time t5 to t6, when signal CLKQ becomes H level, signal ZRDAE changes to L level, and read data buses RD0, RD1, ZRD0, and ZRD1 are disconnected from data buses DB0, DB1, ZDB0, and ZDB1, respectively. The potential difference between read data buses RD and ZRD at this time point is amplified to the maximum amplitude by sense amplifier 420, which is a cross-coupled amplifier.
FIG. 41 is a circuit diagram showing the configuration of parallel/serial converting circuit 1556 in FIG. 38.
Parallel/serial converting circuit 1556 orders data in accordance with signal EZORG. Signal EZORG is a signal determined by the least significant bit CA0 of the column address given together with command READ. When address bit CA0 is 0, signal EZORG is set to H level. On the contrary, when address bit CA0 is 1, signal EZORG is set to L level. Signal EZORG has a role of ordering data so that prefetched 2-bits data corresponds to address bit CA0.
Referring to FIG. 41, parallel/serial converting circuit 1556 includes: a signal generating unit 1820 for generating a control signal in accordance with signal EZORG; data holding circuits 1821 to 1824 for latching data signals transmitted via read data buses ZRD0, RD0, ZRD1, and RD1, respectively; a switching circuit 1826 for switching outputs of data holding circuits 1821 to 1824 in accordance with an output of signal generating unit 1820 in correspondence with an output order; a holding circuit 1828 for holding a signal corresponding to data which is output first among outputs of switching circuit 1826 and driving read data buses RDD and ZRDD; and a holding circuit 1830 for holding data which is output second among outputs of switching circuit 1826 and driving read data buses RDD and ZRDD.
Signal generating unit 1820 includes: an inverter 1922 for receiving and inverting signal EZORG and outputting a signal TR_O; an inverter 1924 for receiving and inverting signal TR_O and outputting a signal TR_E; an inverter 1926 for receiving and inverting signal NZPCNT and outputting a signal PZN; an inverter 1928 for receiving and inverting signal PZN and outputting a signal NZP; an inverter 1930 for receiving and inverting signal DOE and outputting a signal RES; and an inverter 1932 for receiving and inverting signal RES and outputting a signal ZRES.
Signal generating unit 1820 further includes: an NAND circuit 1934 of three inputs for receiving signals CQN, TR_E, and PZN; an NAND circuit 1936 of three inputs for receiving signals CQP, TR_E, and NZP; and an NAND circuit 1938 for receiving outputs of NAND circuits 1934 and 1936 and outputting a signal TR2_E.
Signal generating unit 1820 further includes: an NAND circuit 1940 of three inputs for receiving signals CQN, TR_O, and PZN; an NAND circuit 1942 of three inputs for receiving signals CQP, TR_O, and NZP; and an NAND circuit 1944 for receiving outputs of NAND circuits 1940 and 1942 and outputting signal TR2_O.
Signal generating unit 1820 further includes: an NOR circuit 1946 of three inputs for receiving signals CQP, CQN, and RES; an inverter 1948 for receiving and inverting an output of NOR circuit 1946 and outputting a signal TR23; an inverter 1950 for receiving and inverting signal ZRES; an NOR circuit 1952 for receiving signal CLKQ and an output of inverter 1950 and outputting a signal ZTRV; an inverter 1954 for receiving and inverting signal ZTRV and outputting signal TRV; an NAND circuit 1956 for receiving signals CQP and PZN; an NAND circuit 1958 for receiving signals CQN and NZP; and an NAND circuit 1960 for receiving outputs of NAND circuits 1956 and 1958 and outputting a signal TR3.
Data holding circuit 1821 includes: a clocked inverter 1832 which is activated when signal TRV becomes H level, to invert a data signal transmitted via data bus ZRD0 and output the resultant to a node N111; an inverter 1834 whose input is connected to node N111; and a clocked inverter 1836 which is activated when signal ZTRV becomes H level, to invert an output of inverter 1834, and output the resultant to node N111.
Data holding circuit 1822 is different from data holding circuit 1821 with respect to the point that read data bus RD0 is connected in place of read data bus ZRD0, and the data holding circuit 1822 is connected to a node N112 in place of node N111. Data holding circuit 1823 is different from data holding circuit 1821 with respect to the point that read data bus ZRD1 is connected in place of read data bus ZRD0, and data holding circuit 1823 is connected to a node N113 in place of node N111. Data holding circuit 1824 is different from data holding circuit 1821 with respect to the point that read data bus RD1 is connected in place of read data bus ZRD0, and the data holding circuit 1824 is connected to a node N114 in place of node N111. However, the internal circuit configuration in each of data holding circuits 1823 and 1824 is similar to that of data holding circuit 1821, so that its description will not be repeated.
Switching circuit 1826 includes: an inverter 1838 for receiving and inverting signal TR2_E; an inverter 1840 for receiving and inverting signal TR2_O; a clocked inverter 1842 for inverting a signal transmitted to node N111 in response to activation of signal TR2_O and outputting the resultant to a node N121; a clocked inverter 1844 for inverting a signal transmitted to node N111 in response to activation of signal TR2_E and outputting the resultant to read data bus ZRDD; a clocked inverter 1846 for inverting a signal transmitted to node N112 in response to activation of signal TR2_O and outputting the resultant to node N122; and a clocked inverter 1848 for inverting a signal transmitted to node N112 in response to activation of signal TR2_E and outputting the resultant to read data bus RDD.
Switching circuit 1826 further includes: a clocked inverter 1850 for inverting a signal transmitted to node N113 in response to activation of signal TR2_E and outputting the resultant to node N121; an inverter 1852 for inverting a signal transmitted to node N113 in response to activation of signal TR2_O and outputting the resultant to read data bus ZRDD; a clocked inverter 1854 for inverting a signal transmitted to node N114 in response to activation of signal TR2_E and outputting the resultant to node N122; and a clocked inverter 1856 for inverting a signal transmitted to node N114 in response to activation of signal TR2_O and outputting the resultant to read data bus RDD.
Holding circuit 1828 includes: an inverter 1862 for receiving and inverting signal TR23; an inverter 1858 whose input is connected to read data bus RDD; a clocked inverter 1860 for receiving and inverting an output of inverter 1858 when an output of inverter 1862 becomes H level and outputting the resultant to read data bus RDD; and an N-channel MOS transistor 1864 which is made conductive in accordance with signal RES to connect read data bus RDD to the ground node.
Holding circuit 1828 further includes: an inverter 1868 whose input is connected to read data bus ZRDD; a clocked inverter 1870 for receiving and inverting an output of inverter 1868 when an output of inverter 1862 becomes H level and outputting the resultant to read data bus ZRDD; and an N-channel MOS transistor 1874 which is made conductive in accordance with signal RES to connect read data bus ZRDD to the ground node.
Holding circuit 1830 includes: an N-channel MOS transistor 1882 for connecting node N122 to the ground node in response to activation of signal RES; and a second data latch 1884 for latching data transmitted to node N122. Second data latch 1884 includes an inverter 1890 whose input is connected to node N122; and an inverter 1892 for receiving and inverting an output of inverter 1890 and supplying the resultant to the input of inverter 1890.
Holding circuit 1830 further includes: an inverter 1886 for receiving and inverting signal TR3; and a clocked inverter 1888 for receiving and inverting an output of inverter 1890 when signal TR3 becomes H level and outputting the resultant to read data bus RDD.
Holding circuit 1830 further includes: an N-channel MOS transistor 1902 for connecting node N121 to the ground node in response to activation of signal RES; and a second data latch 1904 for latching data transmitted to node N121. Second data latch 1904 includes: an inverter 1910 whose input is connected to node N121; and an inverter 1912 for receiving and inverting an output of inverter 1910 and supplying the resultant to the input of inverter 1910.
Holding circuit 1830 further includes: an inverter 1906 for receiving and inverting signal TR3; and a clocked inverter 1908 for receiving and inverting an output of inverter 1910 when signal TR3 becomes H level and outputting the resultant to read data bus ZRDD.
FIG. 42 is an operation waveform chart for explaining operation timings of parallel/serial converting circuit 1556 shown in FIG. 41.
Referring to FIGS. 41 and 42, in the period from time t3 to t4, data is transmitted from read data buses RD0, RD1, ZRD0, and ZRD1 to an output part of switching circuit 1826 via data holding circuits 1821 to 1824.
Read data bus ZRD0 will be described. When signal TRV is at H level, clocked inverter 1832 is activated, and data is transmitted to node N111. When signal TR2_E or TR2_O is activated to H level, a signal transmitted to node N111 is transmitted to read data bus ZRDD or node N121.
Signal TRV becomes H level when signal CLKQ is at H level. One of signals TR2_E and TR2_O is activated to H level in accordance with address bit CA0. The activating timing is valid for a period in which signal CQP is at H level when the CAS latency is 2.5.
For example, in the case where CA0 is 0, data on data bus DB0 is output first, and signal TR_E is set to H level, data Dn0 which is output first from the prefetched 2-bits data passes through clocked inverter 1844 via node N111 and is transmitted to read data bus ZRDD in a period Te in FIG. 42. Data Dn1 which is output later passes from read data bus ZRD1 through clocked inverter 1850 via node N113, arrives at node N121, and is held in second data latch 1904.
When signal TR3 is activated to H level in accordance with signal CQN in the period from time t4 to t5, the data held in second data latch 1904 passes through clocked inverter 1908 and is output to read data bus ZRDD.
Data in read data buses RD0 and RD1 is similarly ordered and output to read data bus RDD.
First, in the example of the configuration shown in FIG. 38, between a position where data on the data bus is amplified by amplifying circuit 1554 and a position where the amplified data is output to the outside of the chip, parallel/serial converting circuit 1556 is provided. In the case of parallel/serial converting circuit 1556 shown in FIG. 41, data to be output first in the prefetched 2-bits data is transmitted to read data buses RD0 and ZRD0 via clocked inverters of two stages in parallel/serial converting circuit 1556. For example, in the case where the signal transmitted from amplifying circuit 1554 in FIG. 38 via read data bus ZRD0 corresponds to data which is output first, the data is output to read data bus ZRDD via clocked inverters 1832 and 1844 of two stages shown in FIG. 41.
On the other hand, in the case where read data is read from the memory array each time like an SDR (Single Data Rate) SDRAM, such a parallel/serial converting circuit is unnecessary. Consequently, as compared with the configuration shown in FIG. 38, a data propagation delay in the data output circuit is shorter.
In other words, in the configuration example shown in FIG. 38, the data propagation delay in the data output circuit is large and, as a result, an actual value Tcac of time of a period from command READ is accepted until first data is output from a terminal is long. The inverse which is the number obtained by dividing Tcac by CAS latency CL, that is, CL/Tcac is the actual operating frequency. Long Tcac denotes that the operating frequency cannot be improved.
When a delay in data output circuit 1550 becomes larger, backward amount Ta shown in FIG. 42 of clock signals CLK_P and CLK_N generated by DLL circuit 1500 becomes large as well. In the case where clock signals EXTCLK and EXTZCLK in the clock cycle immediately preceding to a clock cycle in which data is output are delayed to generate internal clock signals, time of tCK-Ta or longer cannot be allowed until the internal clock signal is generated (tCK denotes a clock cycle time). That is, if circuit operation takes time longer than tCK-Ta even when the delay time is set to 0 by DLL circuit 1500, internal clocks have to be generated by using clock signals EXTCLK and EXTZCLK in the cycle preceding to the immediately preceding clock cycle.
Generally, when clock backward amount Ta is large, it is difficult to design the DLL circuit for the reason that a control circuit for dynamically switching clock signals EXTCLK and EXTZCLK in preceding cycles of the proper number in the DLL circuit in order to realize the operation in a wide frequency range becomes complicated.
In addition, the circuit scale of parallel/serial converting circuit 1556 shown in FIG. 41 is large and the layout area is large. As a result, it becomes difficult to design a layout of an output circuit band, and there are adverse influences such that it is difficult to sufficiently assure a decoupling capacity for stabilizing power supply. When the layout area becomes large, the length of signal interconnection between circuits becomes long, and it is feared that an influence of parasitic capacitance is exerted.
An object of the present invention is to provide a very reliable semiconductor memory device with an assured operation margin while avoiding increase in delay in data propagation and increase in layout area.
The invention relates to, in short, a semiconductor memory device including a memory array, a first data bus, and a data output circuit.
From the memory array, a plurality of data signals are read in a group in accordance with a clock signal. The first data bus transmits the plurality of data signals. The data output circuit receives the plurality of data signals from the data bus and amplifies the signals. The data output circuit includes: a plurality of selecting units for selecting corresponding one of the plurality of data signals in accordance with an address signal; a plurality of amplifying units provided in correspondence with the plurality of selecting units, respectively, each for amplifying an output of a corresponding selecting unit; and an output driving circuit for sequentially receiving the plurality of data signals amplified from the plurality of amplifying units.
Therefore, a main advantage of the invention is that data can be output at high speed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.